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龙芯处理器服务器芯片组的适配与实现

郑臣明 姚宣霞 周芳 郑雪峰 杨晓君 戴荣

郑臣明, 姚宣霞, 周芳, 郑雪峰, 杨晓君, 戴荣. 龙芯处理器服务器芯片组的适配与实现[J]. 工程科学学报. doi: 10.13374/j.issn2095-9389.2021.10.08.003
引用本文: 郑臣明, 姚宣霞, 周芳, 郑雪峰, 杨晓君, 戴荣. 龙芯处理器服务器芯片组的适配与实现[J]. 工程科学学报. doi: 10.13374/j.issn2095-9389.2021.10.08.003
ZHENG Chen-ming, YAO Xuan-xia, ZHOU Fang, ZHENG Xue-feng, YANG Xiao-jun, DAI Rong. Adaption and implementation of server chipsets for the Loongson CPU[J]. Chinese Journal of Engineering. doi: 10.13374/j.issn2095-9389.2021.10.08.003
Citation: ZHENG Chen-ming, YAO Xuan-xia, ZHOU Fang, ZHENG Xue-feng, YANG Xiao-jun, DAI Rong. Adaption and implementation of server chipsets for the Loongson CPU[J]. Chinese Journal of Engineering. doi: 10.13374/j.issn2095-9389.2021.10.08.003

龙芯处理器服务器芯片组的适配与实现

doi: 10.13374/j.issn2095-9389.2021.10.08.003
基金项目: 国家重大科技专项“核心电子器件、高端通用芯片及基础软件产品”资助项目(2017ZX01028-102)
详细信息
    通讯作者:

    E-mail: yaoxuanxia@ustb.edu.cn

  • 中图分类号: TP302.1

Adaption and implementation of server chipsets for the Loongson CPU

More Information
  • 摘要: 针对龙芯中央处理器(CPU)无对应高性能服务器芯片组的现状,设计开发了一种为龙芯CPU筛选芯片组的架构,并实现了一种龙芯CPU和芯片组适配的方法。提出了采用现场可编程门阵列(FPGA)串联在龙芯CPU和即将适配的多组芯片组之间的架构。借助于此架构,设计实现了在CPU和芯片组之间待处理物理信号线的连接方法,设计了两者之间上下电时序配合的调试方法,设计实现了规避两者信号协议差异的方法。借助该架构和这些方法能够实现同时筛选多款芯片组的目的,避免了以前需要设计多款主板进行适配的情况,节省了重复研发主板的成本;找到了可以适配龙芯CPU的高性能服务器芯片组;其芯片组规格参数和性能高于目前龙芯CPU所用的芯片组,开拓了其在服务器领域的应用。

     

  • 图  1  龙芯CPU和芯片组之间的适配架构

    Figure  1.  Adaptation architecture between Loongson CPU and chipsets

    图  2  FPGA内部总体架构图

    Figure  2.  Overall architecture of the FPGA

    图  3  包含FPGA和各种芯片组的主板

    Figure  3.  Motherboard sample containing the FPGA various chipsets

    图  4  HT总线调试流程

    Figure  4.  Flow of the HT bus debug

    图  5  HT重要暂不确定控制信号线经适配证明后找到的正确连接方式

    Figure  5.  Appropriate connection of the important but temporarily indeterminate HT signals after effective adaptation

    图  6  经适配证明后找到的正确电源时序

    Figure  6.  Correct power sequence after effective adaptation

    图  7  SR5690+SP5100龙芯双路服务器产品主板

    Figure  7.  Loongson two-way SMP motherboard product using SR5690 + SP5100 chipsets

    表  1  HT总线的连接信号线

    Table  1.   Hyper transport bus link signals

    SignalWidthDescription
    CAD2, 4, 8, or 16Command, addresses, and data (CAD). Carries HyperTransport™ requests, responses, addresses, and data. CAD width can be different in each direction.
    CTL1, 2, or 4Differentiates control and data. Each byte of CAD has a control(CTL) signal in the Gen3 protocol. One CTL signal is used for an entire link in the Gen1 protocol.
    CLK1, 2, or 4Clocks(CLK)for the CAD and CTL signals. Each byte of CAD and its respective CTL signal has a separate clock signal.
    下载: 导出CSV

    表  2  HT总线的复位/初始化信号线

    Table  2.   Reset/Initialization signals of the HT bus

    SignalWidthDescription
    PWROK1Power and clocks are stable
    RESET#1Reset the HyperTransport™ chain
    下载: 导出CSV

    表  3  HT总线的电源管理信号线

    Table  3.   Power management signals

    SignalWidthDescription
    LDTSTOP#1Enables and disables links during system state transitions
    LDTREQ#1Indicates link is active or requested by a device
    下载: 导出CSV

    表  4  芯片组规格对比

    Table  4.   Comparison of different chipset specifications

    ItemFeatures of 7A1000Features of SR5690 + SP5100
    HT busHT3.0 × 16HT3.0 × 16
    PCIE32 lanes42 lanes
    SATA3 × SATA2.06 × SATA2.0
    USB Ports6 × USB2.014 × USB2.0
    RASNoYes
    IOMMUNoYes
    下载: 导出CSV

    表  5  SPEC CPU2006性能对比

    Table  5.   Analysis of SPEC CPU2006 performance

    Serverint_speed_
    base
    int_rate_
    base
    fp_speed_
    base
    fp_rate_
    base
    7A1000 server12.3078.0712.0274.90
    SR5690+ SP5100 server13.0283.6012.8082.60
    Performance improvement/%67610
    下载: 导出CSV

    表  6  IOZone性能对比

    Table  6.   Analysis of IOzone performance

    Server512 Byte read speed/ (MB·s−1)(Average of three results)1 MB read speed/ (MB·s−1)(Average of three results)512 Byte write speed/ (MB·s−1)(Average of three results)1 MB write speed/ (MB·s−1)(Average of three results)
    7A1000 server38.56696.311.25306.76
    SR5690+SP5100 server43.19800.761.53383.45
    Performance improvement/%12152225
    下载: 导出CSV

    表  7  Netperf性能对比

    Table  7.   Analysis of Netperf performance

    ServerTCP Throughput/ (MB·s−1)(Average of three results)TCP
    transfer rate/ (Times·s−1)(Average of three results)
    UDP
    Throughput/ (MB·s−1)(Average of three results)
    UDP
    transfer rate/ (Times·s−1)(Average of three results)
    7A1000 server850.518738.91852.648999.10
    SR5690+SP5100 server935.569787.58946.439989.00
    Performance improvement/%10121111
    下载: 导出CSV
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  • 收稿日期:  2021-10-08
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