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摘要: 针对龙芯中央处理器（CPU）无对应高性能服务器芯片组的现状，设计开发了一种为龙芯CPU筛选芯片组的架构，并实现了一种龙芯CPU和芯片组适配的方法。提出了采用现场可编程门阵列（FPGA）串联在龙芯CPU和即将适配的多组芯片组之间的架构。借助于此架构，设计实现了在CPU和芯片组之间待处理物理信号线的连接方法，设计了两者之间上下电时序配合的调试方法，设计实现了规避两者信号协议差异的方法。借助该架构和这些方法能够实现同时筛选多款芯片组的目的，避免了以前需要设计多款主板进行适配的情况，节省了重复研发主板的成本；找到了可以适配龙芯CPU的高性能服务器芯片组；其芯片组规格参数和性能高于目前龙芯CPU所用的芯片组，开拓了其在服务器领域的应用。Abstract: The CPU is the core part of all integrated circuits. Although some homemade CPUs of proprietary intellectual property rights are rapidly developed, few high-performance chipsets are available, especially in server domains, to match them. Thus, the total systems designed using these CPUs and low-performance chipsets do not have proper performance. The Loongson CPU faces the same problem. To seek better chipsets for it, certain architecture and some methods are designed and implemented to adapt different types of chipsets. In this architecture, a field-programmable gate array (FPGA) is linked between a CPU and these chipsets. An FPGA is divided into three domains: an HT (hyper transport) bus domain, a processing domain for important but temporarily indeterminate signals, and a CPLD (complex programmable logic device) function domain. In these adaption processes, HT bus signals, the temporarily indeterminate signals, and power signals in CPUs and chipsets are respectively linked into three domains in an FPGA and treated by a programming FPGA to perform all types of possible signal combinations. The power sequence between the CPU and chipsets is coordinated to the right order using an FPGA. The signal integrity difference between them is avoided and trimmed to the right state by amending their signals in the FPGA. In this system, the experimental results show that this architecture and these methods simultaneously make more chipsets work together to be adapted than before in a single motherboard. This combination avoids researching and developing many different motherboards for every type of possible chipset and greatly reduces costs. High-performance server chipsets can be found to properly match the Loongson CPU and have better specifications and higher performance than those currently used for the Loongson CPU. A prototype system composed of the Loongson CPU and five types of chipsets is designed and implemented. Using the above architecture and methods, a type of optimal server chipsets SR5690 + SP5100 has been found, and the matching principles or correct settings for the signal connection and power sequence have been concluded. The Loongson 3B4000 two-way SMP motherboard with SR5690 + SP5100 chipsets is also produced. On this motherboard, the results of evaluation experiments on computing performance tests by the SPEC CPU 2006 program, storage performance tests by the IO zone program, and network performance tests by the Netperf program are performed. Compared with the current Loongson 3B4000 server with a 7A1000 chipset, the test results show the performance on three items is improved by approximately 10%. The combination of the Loongson CPU and this type of server chipset provides wider applications in the server market and promotes the development of the Loongson CPU in its ecosystem.
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Key words:
- Loongson /
- chipsets /
- adaption /
- server /
- field-programmable gate array
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图 1 龙芯CPU和芯片组之间的适配架构
Figure 1. Adaptation architecture between Loongson CPU and chipsets
图 5 HT重要暂不确定控制信号线经适配证明后找到的正确连接方式
Figure 5. Appropriate connection of the important but temporarily indeterminate HT signals after effective adaptation
图 7 SR5690+SP5100龙芯双路服务器产品主板
Figure 7. Loongson two-way SMP motherboard product using SR5690 + SP5100 chipsets
表 1 HT总线的连接信号线
Table 1. Hyper transport bus link signals
Signal Width Description CAD 2, 4, 8, or 16 Command, addresses, and data (CAD). Carries HyperTransport™ requests, responses, addresses, and data. CAD width can be different in each direction. CTL 1, 2, or 4 Differentiates control and data. Each byte of CAD has a control(CTL) signal in the Gen3 protocol. One CTL signal is used for an entire link in the Gen1 protocol. CLK 1, 2, or 4 Clocks(CLK)for the CAD and CTL signals. Each byte of CAD and its respective CTL signal has a separate clock signal. 
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表 2 HT总线的复位/初始化信号线
Table 2. Reset/Initialization signals of the HT bus
Signal Width Description PWROK 1 Power and clocks are stable RESET# 1 Reset the HyperTransport™ chain
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表 3 HT总线的电源管理信号线
Table 3. Power management signals
Signal Width Description LDTSTOP# 1 Enables and disables links during system state transitions LDTREQ# 1 Indicates link is active or requested by a device
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表 4 芯片组规格对比
Table 4. Comparison of different chipset specifications
Item Features of 7A1000 Features of SR5690 + SP5100 HT bus HT3.0 × 16 HT3.0 × 16 PCIE 32 lanes 42 lanes SATA 3 × SATA2.0 6 × SATA2.0 USB Ports 6 × USB2.0 14 × USB2.0 RAS No Yes IOMMU No Yes
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表 5 SPEC CPU2006性能对比
Table 5. Analysis of SPEC CPU2006 performance
Server int_speed_
baseint_rate_
basefp_speed_
basefp_rate_
base7A1000 server 12.30 78.07 12.02 74.90 SR5690+ SP5100 server 13.02 83.60 12.80 82.60 Performance improvement/% 6 7 6 10
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表 6 IOZone性能对比
Table 6. Analysis of IOzone performance
Server 512 Byte read speed/ (MB·s−1)(Average of three results) 1 MB read speed/ (MB·s−1)(Average of three results) 512 Byte write speed/ (MB·s−1)(Average of three results) 1 MB write speed/ (MB·s−1)(Average of three results) 7A1000 server 38.56 696.31 1.25 306.76 SR5690+SP5100 server 43.19 800.76 1.53 383.45 Performance improvement/% 12 15 22 25
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表 7 Netperf性能对比
Table 7. Analysis of Netperf performance
Server TCP Throughput/ (MB·s−1)(Average of three results) TCP
transfer rate/ (Times·s−1)(Average of three results)UDP
Throughput/ (MB·s−1)(Average of three results)UDP
transfer rate/ (Times·s−1)(Average of three results)7A1000 server 850.51 8738.91 852.64 8999.10 SR5690+SP5100 server 935.56 9787.58 946.43 9989.00 Performance improvement/% 10 12 11 11
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