Design of ternary adiabatic JKL flip-flops

A design scheme of a novel ternary adiabatic JKL flip-flop was presented by research on multi-valued logic, adiabatic circuits, and the structure and working principle of ternary flip-flops. In the scheme, firstly, the theory of three essential circuit elements was taken as the guide, the component-level expressions of the ternary adiabatic JKL flip-flop were derived, and the corresponding circuit structure was realized by adopting MOS transistors with different thresholds. Secondly, an adiabatic novenary asynchronous counter was further designed by applying the ternary adiabatic JKL flip-flop and the ternary adiabatic literal circuit. Finally, HSPICE simulation results verify that the proposed circuits have correct logic function. Compared with a conventional ternary JKL flip-flop and a novenary asynchronous counter, the average energy consumption of the designed circuits is both saved more than 75%.